ABOUT ME · EDGE AI COMPUTING

Hello, I’m Wenyao Zhao.

I am a graduate student in the integrated M.S.–Ph.D. program in Integrated Circuit Science and Engineering at the Institute of Semiconductors, Chinese Academy of Sciences, advised by Prof. Liyuan Liu. I received my B.Eng. from the School of Microelectronics at Hefei University of Technology.

My work focuses on the architecture and software stack of custom AI processors. I contribute to custom datapaths, ISA extensions, and digital-system verification while building compilation and deployment infrastructure that spans model parsing, hardware-aware quantization, memory planning, instruction mapping, and code generation. This work enables correct and efficient execution of AI workloads on in-house ASICs and FPGA prototypes.

3custom ASICs
algorithm and deployment work
2FPGA accelerators
designed and verified
2peer-reviewed papers
on algorithms and accelerators

EDUCATION

Education

University of Chinese Academy of Sciences · Institute of Semiconductors, CAS

Integrated Circuit Science and Engineering, combined M.S.–Ph.D. program(recommendation for graduate study without examination) · Beijing, China

Hefei University of Technology · National Exemplary School of Microelectronics

B.Eng. in Integrated Circuit Design and Integrated Systems · Hefei, China

SKILLS & TOOLKIT

Skills & Toolkit

Architecture, compiler, and verification capabilities for custom AI processors

01

AI Processors & Digital Systems

RISC-V custom ISA extensions, SIMD and systolic arrays, compute dataflows, fixed-point datapaths, accelerator integration, and RTL design

02

Compilation & Deployment for Custom Processors

ONNX graph parsing, operator fusion, static memory planning, tensor-layout transformation, instruction mapping, and code generation

03

Hardware-Aware Model Optimization

CNN / Transformer adaptation, fixed-point numerical modeling, operator constraints, pruning, QAT / PTQ, and knowledge distillation

04

Verification & Performance Analysis

MATLAB reference models, VCS RTL simulation, FPGA prototyping and board-level testing, numerical consistency checks, and cycle / memory-bottleneck analysis

Development environmentVerilog / SystemVerilog · VCS / ModelSim · DC · ICC · Vivado · Python / PyTorch · MATLAB · C / C++ · Git / Linux

SELECTED PROJECTS

Selected Projects

End-to-end work across models, compilers, and hardware
Edge AI Accelerator with Custom RISC-V Matrix-Multiplication Instructions

2026.02 - 2026.03Sole Developer

Edge AI Accelerator with Custom RISC-V Matrix-Multiplication Instructions

Designed and implemented a tightly coupled edge-AI coprocessor for the open-source Hummingbird E203, integrating custom matrix-multiplication instructions with a weight-stationary systolic array to explore hardware–software co-design for AI MCUs.

  • HW-SW Co-Design
  • Quantization
  • Systolic Array

PUBLICATIONS

Publications

  1. 2024
    An Energy-Efficient Dehazing Neural Network Accelerator Based on E2 AOD-Net

    Zhihao Zhang, Gaoming Du, Zhenmin Li, Qingran Kang, Wenyao Zhao, Xiaolei Wang · Journal of Real-Time Image Processing, 21(6): 197 · JCR Q2, IF 3.0

  2. 2024
    An Overview of Joint Optimization Methods for Neural Network Compression

    Xin Ning, Wenyao Zhao, Yixin Zong, et al. · CAAI Transactions on Intelligent Systems, 19(1): 36–57 · PKU Core, CCF-C

HONORS

Honors & Awards

  1. Merit Student, University of Chinese Academy of Sciences
  2. President's Award, HFUT; Outstanding Graduate of Anhui Province
  3. National Scholarship; First-Class Scholarship; Outstanding Merit Student, HFUT
  4. Third Prize, National College Student Integrated Circuit Innovation and Entrepreneurship Competition, Central China Division
  5. First Prize, Anhui Provincial Robotics Competition, MCU and Embedded Systems Track
  6. First-Class Scholarship and Merit Student, HFUT
  7. Second-Class Scholarship and Merit Student, HFUT